Advances in integrated circuit technology have progressed dramatically since the integrated circuit (IC) was first successfully implemented in the early 1960s. Improvements in equipment and refinements in processing techniques have allowed the fabrication of ever smaller and more densely packed ICs. For example, while IC feature sizes of a few microns were once considered extraordinary, state of the art technologies are now capable of producing ICs having nanometer scale feature sizes. The ability to scale feature sizes of an IC to smaller dimensions is beneficial since it increases the possible operating speed, reduces power consumption, and lowers the cost per IC unit.
Although scaling provides many benefits, the physical features of an IC become more sensitive to process variations the more the IC is scaled. Physical variations translate into variations in power and performance of the same design among lots, wafers and dies. Significant variations in power and performance are undesirable, since they result in wide deviations in intended circuit performance. The variations also adversely affect the desired yield. While transistors and circuits on smaller scale ICs do not always show significant power and performance variations among dies, such variations can be significant in very large scale integrated (VLSI) circuits. Indeed, variations in performance and power consumption of transistors and other devices within a single VLSI die (i.e., “within-die” variations) can become significant when scaling is pushed to its limits.
Various techniques have been proposed to reduce the impact of process variations on device performance and power consumption. One approach that helps to tighten the distribution of maximum operating frequency fmax (a measure of device performance) and maximum power consumption Pmax among dies, and thereby improve yield, is to apply an “adaptive body bias” (ABB) to the bodies of the IC transistors during operation. Applying an ABB adjusts the threshold voltage of the transistors of the IC in a manner that narrows the distribution of operating frequency and power among dies. A primary drawback of the ABB approach, however, is that additional power distribution networks must be patterned on the dies in order to route the body voltages to the many transistors of the IC. These additional routing resources consume valuable silicon area and add to the overall cost of the IC.
Another technique that addresses the impact of process variations on scaled ICs is the “adaptive supply voltage” (ASV) approach. Similar to the ABB approach, the ASV approach adjusts the supply voltage to the integrated circuit with the object of satisfying predetermined performance and power specifications. An added benefit of the ASV approach over the ABB approach is that no additional power distribution resources are needed to route the supply voltage. In some applications, ASV is applied dynamically, so that power consumption can be decreased or increased depending on a set of timing constraints. This dynamic ASV approach has been shown to be useful in microprocessor chips, where the supply voltage of the microprocessor is dynamically adjusted by built-in firmware or circuitry to conserve power during times when the microprocessor is idle and to increase power during times when the microprocessor is executing a large number of instructions.
While the ABB and ASV approaches do help in improving the yield of scaled ICs, an end user has little control over the performance and power consumption of the product. Typically an end user is provided with only a discrete set of frequency or power consumption specifications (e.g., min, max, nominal) for a given class of products, and corresponding supply voltage ranges that will guarantee that the discrete specifications for products within the class are satisfied. Application of ABB or ASV may then be applied to ensure that products within the class operate somewhere within the bounds of the minimum and maximum specifications.
The prior art methods of providing discrete performance and power consumption specifications, and applying ABB or ASV, do help to ensure that an IC will operate properly somewhere within the specified performance and power limits. However, because the specifications cover a group or class of parts having varying performance and power consumption characteristics, an end user is not provided the flexibility or necessary information to optimize the performance and power consumption of an individual end product, i.e., on a part-by-part basis. Instead, the user is only ensured that a given part will operate somewhere between the minimum and maximum specifications. Further, whereas application of an ABB or ASV does help to ensure that parts from within the given group or class of parts operate within certain specified performance and power ranges, neither of the approaches provides the user the necessary means to ensure that the supply Vdd and/or body bias Vbb voltages applied to any particular part results in optimized or predetermined power consumption and performance.